Electronic systems are becoming a staple of modern life. These electronic systems may be very simple systems, such as individual logic gates that are used for simple control circuits, moderately complex systems, such as integrated logic circuits that are used for controllers and embedded processors, or much more complex systems utilized in powerful computing architectures.
Almost universally, the frequency and power requirements for these electronic systems have been increasing. This is especially true when referring to microprocessor based computing systems. Besides the display, the largest consumer of power in a computing system is the CPU microprocessor, and the higher the clock frequency of the microprocessor, the greater that microprocessor's power consumption (all other aspects being equal). As the power consumption and frequency of semiconductor devices grows so does the simultaneous switching noise (SSN) induced by the switching of the internal circuits of the semiconductor's core logic. This SSN is problematic, as it may cause interference with other aspects of the semiconductor's operation, with associated logic in other portions of the semiconductor, or with a device in which the semiconductor is utilized.
An effective way of suppressing this noise is to attach decoupling capacitors to the semiconductor, or a package containing the semiconductor. Because inductance and resistance between a semiconductor and its power source contributes significantly to the SSN, in most cases the closer decoupling capacitors are attached to a semiconductor device the smaller the SSN will be. FIG. 1 depicts a hierarchy of positions for the attachment of decoupling capacitors. Ideally, decoupling capacitors 110 will be coupled as closely to semiconductor 120 on package 130 as possible.
Additionally, the effectiveness of these decoupling capacitors is partially determined by how large the equivalent series inductance (ESL) and equivalent series resistance (ESR) are between the semiconductor and the decoupling capacitors. These factors are influenced, in main, by two variables: the type of decoupling capacitors used, and the path between these capacitors and the semiconductor in question.
To minimize the former variable, various low ESL and ESR decoupling capacitors are available from assorted vendors such as AVX, Murata and TDK. However, to minimize the latter variable is more difficult. Attaching the capacitors close to the semiconductor is one possible solution. To accomplish this, in many cases high-end microprocessors have decoupling capacitors coupled to the bottom side of the package with which they are utilized, usually just beneath the die to which the microprocessor is attached. FIG. 2 depicts one example of a method of attaching decoupling capacitors in close proximity to a semiconductor. Die 310 containing an integrated circuit, such as a microprocessor, is attached to substrate 220. BGA balls 230 serve to couple die 310 to a power source or other signal lines. Decoupling capacitors 380 may also be attached to the side of substrate 220 opposite die 310, placing them in close proximity to die 310.
Typically, substrate 220, with which microprocessors or semiconductors are packaged, is made of organic material (such as epoxy resin). Substrate 220 may be fabricated using build-up technology, which enables higher wiring capability by having fine-line build-up layer(s) on both sides of a coarser core substrate.
FIG. 3 illustrates a cross-sectional schematic of a package with an organic substrate 220. Package 300 consists of die 310 C4 bumps 320 build-up-layers 330, solder resist layers 340, microvias 350, core layer 360, plated through holes 370, and decoupling capacitors 380. Decoupling capacitors 380 are electrically coupled to the remainder of the package through pads in solder resist layer 330 of substrate 220. These pads are usually of a single polarity and are isolated from one another by solder resist. A terminal of decoupling capacitor 380 may be attached to one of these pads, usually by soldering. In package 300, therefore, the electrical path between operating device on die 310 and decoupling capacitors 380 flows through C4 bumps 320, microvias 350, plated through holes 360, microvias 350, pads in solder resist layer 340 to decoupling capacitors 380.
FIGS. 4A, 4B and 4C depict examples of decoupling capacitors for use with a semiconductor package like that pictured in FIG. 2. Decoupling capacitor 400 may have eight terminals 410–480 as pictured in FIG. 4A, and these terminals 410–480 may be of alternating polarity (i.e. interdigitated), as depicted in FIG. 4B. Two capacitors may have terminals with point symmetry to one another as depicted in FIGS. 4B and 4C. As can be seen, identical terminal 410-480 have opposite polarity in these capacitors. In one embodiment, capacitor 400 may be a four capacitor array. In other embodiments, capacitor 400 may be an interdigitated capacitor of the type manufactured by AVX, Murata and TDK.
FIG. 5A shows a typical pad opening layout for use in attaching decoupling capacitor 400 to a substrate. Pad openings 510–580 must be large enough for soldering one terminal 410–480 of decoupling capacitor 400. Recently, however, as the power consumption and frequency of semiconductors has increased, there has been a commensurate need for more decoupling capacitors 400 in a given package 300. Thus, to accommodate a higher density of decoupling capacitors 400, pad openings 510–580 have begun to shrink, as depicted in FIG. 5B. As a result of this shrinking pad opening 510–580 size, the number of microvias 350 contacting pad openings 510–580 has decreased. Not only does this decrease the mechanical reliability of pads and pad openings 510–580, but it also increases the ESR and ESL of the complete electrical path, the very problem trying to be avoided.
To help ameliorate these electrical and mechanical issues, a pad structure akin to the one depicted in FIG. 6 may be used. Pads 610–680 exist in solder resist layer 640. One pad opening 642 exists in each pad 640 for attaching terminals 410–480 of decoupling capacitor 400. One terminal 410–480 is attached to each soldering area of pad opening 612–682 within pad 610–680 having polarity matching terminal 410–480 being attached. Pad openings 612–682 may be defined on pad 610–680 by overlaying a solder mask layer on pads 610–680 during manufacturing of a package.
Using this pad structure, pads have been laid out in a solder resist layer of a substrate as depicted in FIG. 7. Pads 710, 720, 730 having alternating polarity, are laid out in solder resist 740. One pad opening 712, 722, 732 exists within each pad 710, 720, 730 for the coupling of a terminal 410–480 of decoupling capacitor 400 with corresponding polarity. Each pad 710, 720, 730 is separated from every other pad 710, 720, 730 by solder resist 740. Consequently, each pad 710, 720, 730 on substrate has only one pad opening 712, 722, 732.
Decoupling capacitor 400 of the type depicted in FIG. 4A may be attached on the back side of a substrate using this pattern of pads and pad openings with alternating polarity as shown in FIG. 8. Terminals 410–480 of capacitor 400 are attached to pad openings 812–882 of pads 810–880 with matching polarity. This solution, however, conflicts with the need for a high density of decoupling capacitors 400. Pads 810–880 are usually larger than pad openings 812–882 and must be isolated from one another by solder resist 890. Usually, 100–200 microns exists between individual pads 810–880. Consequently, in a given area, decoupling capacitors 400 may only be coupled to a substrate in as close a proximity to one another as the separation between individual pads 810–880 and their corresponding openings 812–882 allow.
Thus, a need exists for mechanically reliable methods and systems for attaching decoupling capacitors to a package which allow a high density of decoupling capacitors to be attached to a package while simultaneously decreasing both the ESL and ESR of the electrical path.